FIG. 1 shows an integrated semiconductor memory device 100 with a memory cell array 10 in which memory cells are arranged in the form of a matrix along the word and bit lines. The memory cell array includes a first sense amplifier SA1 which is connected on both sides to bit lines of a bit line pair BLP1. The bit line pair BLP1 includes a true bit line BLT and a complement bit line BLC. A DRAM (dynamic random access memory) memory cell SZ1 is connected to the true bit line BLT. The memory cell SZ1 includes a storage capacitor SC which is connected to the true bit line BLT via a selection transistor AT. The selection transistor AT can be controlled to conduct by a control signal on the word line WL so that the storage capacitor SC is conductively connected to the true bit line BLT.
Apart from the first sense amplifier, the memory cell array 10 includes a second sense amplifier SA2 which is connected on both sides to a bit line pair BLP2. The bit line pair BLP2 includes a true bit line BLT′ and a complement bit line BLC′. A memory cell SZ2 which is also controlled by a control signal on the word line WL is connected to the true bit line BLT′.
To control a read or write access of one of the memory cells of the memory cell array 10, a control circuit 20 is provided. The control circuit 20 includes a control terminal S20 for applying control signals. A write or read access takes place depending on the applied control signals WR or RD. The integrated semiconductor memory device also includes an address register 30 having an address terminal A30. One of the memory cells of the memory cell array 10 can be selected for the read or write access by applying an address signal which includes an address part X and an address part Y. During this process, the address part X selects a word line whereas the address part Y selects one of the bit line pairs. As a result, it is possible to select the memory cell which is located at the point of intersection of the selected word line with the selected bit line pair.
When an information item is written into the memory cell SZ1, the address of the memory cell SZ1 is applied to the address terminal A30. After that, a write command WR is applied to the control terminal S20 and a data item D with a logical Low or High level is applied to the data terminal DQ. In the case of a logical High level, the sense amplifier SA1 feeds a high voltage potential VBH to the true bit line BLT and a low voltage potential VBL to the complement bit line. In the case of a logical Low level, the sense amplifier SA1 feeds in the low voltage potential VBL on the true bit line BLT and the high voltage potential VBH on the complement bit line BLC. The word line is driven by the control circuit 20 in such a manner that the selection transistor AT is switched into the conducting state. Thus, a first memory state with a high level of a cell voltage or a second memory state with a low level of the cell voltage can be stored in the storage capacitor SC in accordance with the high or low voltage potential on the bit line BLT.
Before and after a read and write access, the bit lines BLT and BLC are charged up to a level of a precharging voltage VEQ during a precharging process. The level of precharging voltage is between the level of the high voltage potential VBH and the level of the low voltage potential VBL.
When the memory state or, respectively, the cell voltage of the memory cell SZ1 is read out, a corresponding address signal for selecting the memory cell SZ1 is applied to the address terminal A30. A read command RD is applied to the control terminal S20 of the control circuit 20. As a result, the word line WL is driven with a high level of a control voltage so that the selection transistor AT of the memory cell SZ1 is controlled to conduct. When a high level of the cell voltage has been stored in the memory cell SZ1, an increase in potential is produced on the true bit line BLT with respect to the precharging voltage VEQ. If, in contrast, a low level of the cell voltage has been stored in the memory cell SZ1, a decrease in potential compared with the precharging voltage VEQ is produced on the true bit line BLT. The complement bit line BLC, in contrast, remains at the level of the precharging voltage VEQ to which it has been charged up after the write access.
The first sense amplifier SA1 evaluates the potential difference between the true bit line BLT and the complement bit line BLC and generates a Low and High level complementary to one another on the data lines DL and /DL. The two complementary levels are again amplified by a secondary sense amplifier, not shown in FIG. 1, so that the data item D is output with a logical Low or High level to the data terminal DQ.
When the level of the cell voltage of the memory cell to be read out is above a level of a threshold voltage of the sense amplifier, the data item D is generated with the logical High level at the data terminal DQ. If, in contrast, the level of the cell voltage of the memory cell to be read out is below a level of the threshold voltage of the sense amplifier, the data item D is generated with the logical Low level at the data terminal DQ.
FIG. 2 shows potential variations on a true and complement bit line during the reading-out of a memory cell, the storage capacitor of which is charged up to a low cell voltage. Before the actual reading process, the two bit lines are charged up to the precharging voltage DQ. At time t1, a control voltage is fed in by the control circuit 20 on the word line connected to the memory cell to be read out. As a result, all memory cells along the word line are activated by their selection transistors being controlled to conduct. Due to the low cell voltage in the example of FIG. 2, a decrease in potential compared with the level of the precharging voltage VEQ occurs on the true bit line BLT. The complement bit line BLC is still charged to the level of the precharging voltage originating from the precharging process.
At time t2, the different potential states on the true bit line BLT and the complement bit line BLC are evaluated by the connected sense amplifier. Since the voltage level on the true bit line BLT is below the level of the precharging voltage on the complement bit line, a decrease in potential to the voltage potential VBL, which, for example, corresponds to a voltage of 0 volts, occurs on the true bit line BLT. In consequence of the evaluation process by the sense amplifier, an increase in potential to the high voltage potential VBH, for example to a voltage of 1.2 volts, occurs on the complement bit line BLC.
The sense amplifier forwards the low voltage level VBL of the true bit line BLT to the data line DL. The high voltage level VBH of the complement bit line BLC is forwarded to the complementary data line /DL. The high and low voltage level are supplied via the two data lines to the secondary sense amplifier which ultimately generates at the data terminal DQ a data item with a logical Low level which corresponds to the memory state in the memory cell.
The evaluation characteristic of a sense amplifier, illustrated in FIG. 2, is dependent on various factors. For example, the magnitude of the increase in potential or decrease in potential on the bit line is dependent on the length of the bit lines and thus on the bit line resistance and bit line capacity. For example, the same cell voltage leads to different increases or decreases in potential compared to the level of the precharging voltage on different bit lines. Furthermore, the layout of the sense amplifier connected to a bit line pair is of decisive significance. Within a memory cell array, the sense amplifiers differ, for example, due to different implants, due to different doping profiles and due to the proximity and orientation with respect to substrate wells of adjacent components. The sense amplifiers of a memory cell array therefore have different electrical characteristics which leads to different evaluation performance with respect to the cell voltage during a read process. The level of the threshold voltage at which a sense amplifier evaluates a cell voltage potential with a logical Low or High level at the data terminal is thus dependent, on the one hand, on the layout of the sense amplifier and, on the other hand, on influences of the circuit environment.
FIG. 3 shows the performance of first sense amplifiers SA1 and second sense amplifiers SA2 of a memory cell array which differ from one another in their layout, during the evaluation of various cell voltages Vwrite. For example, different cell voltage levels are stored in the memory cells in that various voltage levels between 0 and 1.2 volts are applied to a contact pad TP which, for example, is accessible to an external test device at wafer level. The number of memory cells which have been evaluated with a logical High level instead of with a logical Low level during the reading-out by the connected sense amplifiers is plotted.
In the first test step, a particular voltage level, for example 0 volts, is applied to the contact pad TP and fed in on the connected bit lines via the sense amplifiers. After the activation of the memory cells, a low cell voltage is stored in them. During a subsequent read process, the stored cell voltage is evaluated again by the sense amplifiers and the corresponding logical Low or High level is generated at the data terminal DQ. A test device detects the occurrence of the logical Low level at the data terminal DQ.
During the evaluation of a cell voltage of 0 volts, the memory state in almost all memory cells is evaluated correctly by the first sense amplifiers SA1. Thus, not many memory cells fail. In the test steps then following, the cell content is evaluated by the first sense amplifiers, a higher cell voltage being stored in the memory cells during each test step. Above a cell voltage of approx. 0.4 volts, the memory content of approximately 1×105 memory cells is evaluated with the logical High level at the data terminal DQ by the first sense amplifiers. The more the cell voltage is rising in the subsequent test steps, the more memory cells are evaluated with the logical High level by the first sense amplifiers SA1. Above a cell voltage of 0.6 volts, the first sense amplifiers generate a data item with the logical High level at the data terminal G2 during the reading-out of almost all memory cells.
The second sense amplifiers SA2 generate the logical Low level at the data terminal DQ for almost all of the memory cells connected to them up to a cell voltage of approx. 0.6 volts. The higher the cell voltage is above 0.6 volts, the more memory cells are evaluated with the logical High level by the second sense amplifiers. Above a cell voltage of approximately 1 volt, the second sense amplifiers generate the logical High level at the data terminal DQ during the reading-out of almost all memory cells connected to them.
The two curves of FIG. 3 showing the evaluation performance of the first and second sense amplifiers deviate from one another. Depending on whether they belong to a first type of sense amplifier or to a second type of sense amplifier, the sense amplifiers exhibit a different evaluation performance of cell voltages.